High-speed DAC and ADC circuitry of the present applicant is typically characterised in that it is necessary to transmit (distribute) many very-fast clock signals over a relatively long distance, and then receive and employ those clock signals.
FIG. 1 is a schematic diagram showing parts of combined DAC and ADC circuitry 10, as an example of circuitry in which the present invention may be employed. Circuitry 10 comprises ADC circuitry 100 shown on the left-hand side. DAC circuitry 200 shown on the right-hand side, and clock generation and distribution circuitry 300 shown in the middle.
DAC circuitry 200 comprises a switching circuit 210, which comprises clock-controlled circuitry and the data-controlled circuitry. Switching circuit 210 is operable based on input data and clock signals to output an analogue signal representative of the input data.
As a running example, a desired DAC sample rate of 64 Gs/s is assumed, with time-interleaved data signals DATA 1 to DATA 4 (corresponding to the four input data signals shown) input to the switching circuit 210 being 16 GHz (i.e. time-interleaved) data signals. The four input clock signals CLK φ1 to CLK φ4 are assumed to be four time-interleaved 16 GHz clock signals, which are substantially sinusoidal (raised-cosine signals).
Three stages of multiplexing/retiming 220, 230 and 240 are also shown by way of example, in order to input at the first multiplexed/retiming circuit 240 a parallel set of 64 1 GHz data signals when retiming is carried out (or a parallel set of 128 500 MHz signals, when multiplexing is carried out), and output those as a parallel set of 64 1 GHz data signals to the second multiplexer 230, which in turn outputs 16 4 GHz signals to the third and last multiplexer 220, which in turn outputs the time-interleaved data signals DATA 1 to DATA 4 as 4 16 GHz signals as above.
The data signals may be differential data signals, in which case circuitry 210, 220, 230 and 240 may also be differential circuitry.
The switching circuit 210 is representative of a single segment or “slice” in the overall DAC 200. Thus, any coding (e.g. thermometer-coding) of an ultimate input digital signal is assumed to have occurred upstream of the digital signals input in FIG. 1, such that those input digital signals input are only those intended for the segment or slice shown.
The overall DAC 200 would have further slices or segments, each with their own stages of multiplexing/retiming 220, 230 and 240. Of course, the clock generation and distribution circuitry 300 may be shared (at least in part) between the segments (or separately provided, at least in part).
The analogue outputs of the various slices or segments may be combined to create a single analogue output of the overall DAC. For example, seven segments could be provided to produce the outputs for the 3 MSBs of an 8-bit DAC (with thermometer-encoding), and five segments (in which their outputs are binary weighted) could be provided to produce the outputs for the 5 LSBs. Other variations would of course be possible. For example, an impedance ladder could be employed, as disclosed in EP-A1-2019490.
Clock generation and distribution circuitry 300 comprises a clock generator 310 configured to generate the time-interleaved clock signals CLK φ1 to CLK φ4 and supply them to the switching circuit 210. Further, shown are three stages of clock generation 320, 330, 340, in order to take the input clock signals CLK φ1 to CLK φ4 and generate in turn the clock signals (4 GHz and 1 GHz) required by the three stages of multiplexing/retiming 220, 230, 240, as indicated in FIG. 1. Although the clock signals CLK φ1 CLK φ4 generated by clock generator 310 are sinusoidal, the clock signals generated by the three stages of clock generation 320, 330, 340 need not be, and may be switched-logic signals.
In a similar manner, the ADC circuitry 100 comprises sampler circuitry 110. Sampler circuitry 110 is operable based on input clock signals CLK φ1 to CLK φ4 and an input analogue current signal to output by current steering four time-interleaved streams of current pulses representative of the input signal. Again, either single-ended or differential signals could be used.
A similar running example is employed here, i.e. a desired ADC sample rate of 64 Gs/s, and with 2-stages of demultiplexing shown as 120 and 130, each performing 1:4 demultiplexing, and with sub-ADC units 140. The sampling circuitry is configured to take samples from the analogue input at the overall 64 Gs/s sample rate by current steering in current mode, and to output 4 streams (single-ended or differential) each at 16 Gs/s (which may be expressed herein as 16 GHz), with the first demultiplexing stage 120 outputting 16 4 Gs/s signals, and with the second demultiplexing stage 130 outputting 64 1 Gs/s signals.
The same clock generation and distribution circuitry 300 accordingly provides its clock signals to the ADC circuitry 100, as well as to the DAC circuitry 200. In particular, looking at FIG. 1 and working downwards from the sampler circuitry 110 and switching circuitry 210, in both the DAC and ADC circuitry the signals in successive stages are 4 16 GHz signals, then 16 4 GHz signals, and then 64 1 GHz signals.
For a more detailed understanding of the circuitry of FIG. 1, reference may be made to EP-A1-2211468 which discloses ADC circuitry in line with ADC circuitry 100.
However, the important point to note is that the FIG. 1 circuitry comprises a large number of very fast dock signals, for example including the 16 GHz signals CLK φ1 to CLK φ4 and of 4 GHz and 1 GHz signals.
Such signals need to be distributed from a PLL (phase lock loop) or other clock signal generator (see clock generator 310) where they are generated to the sampler circuitry 110 and switching circuitry 210. Additionally, many fast clock signals (e.g. 4 GHz and 1 GHz) are required by the DEMUX (demultiplexers) 120, 130 and sub-ADC units 140 in the ADC circuitry 100 and the MUX (multiplexers or retimers) 220, 230, 240 in the DAC circuitry 200. Again, these clock signals need to be distributed to the necessary circuitry elements (e.g. transistors thereof) via transmission lines from the clock generation and distribution circuitry 300 where they are generated.
A problem is that the signal transmission lines (tracking, in integrated circuitry e.g. on an IC chip) have inherent parasitic capacitance, and that the transmission of such a large number of very fast clock signals (clocks) over a long distance leads to power consumption issues.
For example, it is typically unusual to have so many high-speed clocks driving so many circuits; normally if there are many circuits (e.g. in a DSP core) there are few clocks, and if there are many clocks (e.g. in RF circuits) they each go to only a small number of places and are distributed over a relatively small distance. The circuitry 10 of FIG. 1 is effectively a worst-case combination in which very high-speed ADCs and DACs rely on interleaving or multiplexing the operations of many lower-speed (but nevertheless fast) circuits, and in which there is thus the requirement to distribute a large number of very fast clock signals to many functional elements.
For example, it may be considered that:                Power is proportional to C·V2·F·N        
where:                C=parasitic capacitance of tracking used to distribute clock signals        V=peak-to-peak voltage of the clock signals        F=frequency of the clock signals        N=the number of transmission lines        
Essentially, C, F and N are large for the circuitry of FIG. 1, and it is difficult to avoid that in such circuitry. Also, the voltage V has a squared effect as above.
FIG. 2(a) presents a first conventional method of transmitting a pair of input differential (inverse or complementary) clock signals, here shown generically as IN and /IN. As shown, CMOS buffer circuitry 410 is provided at both the transmitting (TX) and receiving (RX) sides, where each comprises a pair of series-connected CMOS buffers (inverters) per input signal, or a pair of differential CMOS buffers shared by the input signals.
The two sets of buffer circuitry 410 are connected via a pair of transmission lines 420 as shown, an as to carry buffered differential signals between them. The transmission lines have their parasitic capacitances 430 explicitly shown.
The CMOS buffer circuitry 410 comprising CMOS buffers may itself be considered relatively low power (as is well known), however the voltage swing on the transmission lines 420 over the indicated parasitic capacitances 430 (e.g. ΔV=900 mV) is relatively high leading to high power consumption over the transmission lines 420 themselves. This “local” low-power consumption, hut high-power consumption in transmission, is indicated in FIG. 2(a).
FIG. 2(b) presents a second conventional method of transmitting a pair of differential (inverse or complementary) clock signals, here again shown generically as IN and /IN, using Common Mode Logic (CML) buffer circuitry 440 at both the transmitting and receiving sides. The two sets of CML buffer circuitry 440 are similarly connected via a pair of transmission lines 420 as shown, so as to carry buffered differential signals between them. The transmission lines have their parasitic capacitances 430 explicitly shown.
The advantage of the CML buffer circuitry 440 is reduced voltage swing (e.g. ΔV=200 mV) over the transmission lines 420, however there is relatively high power consumption in the CML buffer circuitry 440, because with e.g. 900 mV input signals, and with VOUT=200 mV, there is 700 mV lost in the CML buffers. This “local” high-power consumption, but low-power consumption in transmission, is indicated in FIG. 2(b).
Thus, the CMOS approach of FIG. 2(a) may be described as having low local power consumption and high power consumption in transmission, whereas the CML approach of FIG. 2(b) has high local power consumption and low power consumption in transmission. Unfortunately, both approaches lead to high overall power consumption if deployed in for example the circuitry 10 of FIG. 1, given the sheer number of clock signals to be distributed, and the large distance (i.e. large parasitic capacitance) over which they need be distributed.
It is desirable to solve some or all of the above problems.